Issues

• Signed 8/16-bit NEON left-shift helpers invoke C undefined behavior

  renode/renode#1070 · Filter by author canxin121 opened on Nov 6, 2026

• AArch64 FP64-to-FP16 conversion bypasses required rounding and exceptions

  renode/renode#1069 · Filter by author canxin121 opened on Nov 6, 2026

• A32 tiny FP32-to-FP16 inputs ignore directed rounding to minimum subnormal

  renode/renode#1068 · Filter by author canxin121 opened on Nov 6, 2026

• A32 IEEE FP16 NaN conversion loses sign/payload or fails to quiet NaN

  renode/renode#1067 · Filter by author canxin121 opened on Nov 6, 2026

• A32 IEEE FP16 conversion returns infinity for every overflow rounding mode

  renode/renode#1066 · Filter by author canxin121 opened on Nov 6, 2026

• A32 AHP half conversion raises extra Underflow/Inexact on finite overflow

  renode/renode#1065 · Filter by author canxin121 opened on Nov 6, 2026

• A32 AHP FP32-to-FP16 NaN conversion fails to raise Invalid Operation

  renode/renode#1064 · Filter by author canxin121 opened on Nov 6, 2026

• Cortex-A15 VFP feature flags omit required VFP/VFP3 and expose missing CPACR checks

  renode/renode#1063 · Filter by author canxin121 opened on Nov 6, 2026

• stm32f746.repl: timers clocked at 10 MHz, missing UART4/5/7/8, IWDG and CRC, RAM size 384 KiB instead of 320 KiB

  renode/renode#1062 · Filter by author philippecottier opened on Nov 4, 2026

• STM32SPI (F7 series): 16-bit write to DR in 8-bit frame mode sends one byte instead of two (data packing)

  renode/renode#1061 · Filter by author philippecottier opened on Nov 4, 2026

• A32 UASX/USAX produce incorrect GE flags for unsigned halfword lanes

  renode/renode#1058 · Filter by author canxin121 opened on Nov 2, 2026

• A32 VCVT to unsigned fixed-point incorrectly adds IXC for an invalid negative input

  renode/renode#1057 · Filter by author canxin121 opened on Nov 2, 2026

• Renode spuriously sets FPSCR.OFC for AArch32 vector fixed-point conversion

  renode/renode#1056 · Filter by author canxin121 opened on Nov 2, 2026

• A32 FP32-to-FP16 conversion reports incorrect FPSCR exception flags

  renode/renode#1055 · Filter by author canxin121 opened on Nov 2, 2026

• A32 UHSUB8 computes halving differences across byte lanes

  renode/renode#1054 · Filter by author canxin121 opened on Nov 2, 2026

• A32 MCRR to an unallocated CP15 64-bit register does not raise Undefined

  renode/renode#1053 · Filter by author canxin121 opened on Nov 2, 2026

• Renode AArch32 VMAX/VMIN return a numeric operand when an input is NaN

  renode/renode#1052 · Filter by author canxin121 opened on Nov 2, 2026

• A32 saturating SIMD instructions fail to export FPSCR.QC

  renode/renode#1051 · Filter by author canxin121 opened on Nov 2, 2026

• AArch32 VABAL.S32 sign-extends absolute differences that overflow before widening

  renode/renode#1050 · Filter by author canxin121 opened on Nov 2, 2026

• AArch32 signed rounded Advanced SIMD shifts return sign fill for large right shifts

  renode/renode#1049 · Filter by author canxin121 opened on Nov 2, 2026

• AArch32 unsigned Advanced SIMD variable shifts mishandle counts with magnitude 32 or greater

  renode/renode#1048 · Filter by author canxin121 opened on Nov 2, 2026

• STM32F7_USART crashes Renode when PS, PCE or STOP is written while the USART is enabled

  renode/renode#1047 · Filter by author 60north opened on Nov 1, 2026

• ARM MVE VSTRD scatter stores clobber the next 32-bit word (DO_VSTR64_SG store width)

  renode/renode#1046 · Filter by author bergmorten opened on Oct 31, 2026

• STM32DMA: stream write offset not reset when a stream is re-enabled

  renode/renode#1045 · Filter by author bergmorten opened on Oct 31, 2026
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• Verilated cpu_ibex cosimulation does not build with latest Renode

  renode/renode#1044 · Filter by author Arusekk opened on Oct 30, 2026