RTL implementation of a performance/area optimized bfloat16 adder and multiplication.
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Updated
Mar 28, 2026 - Verilog
RTL implementation of a performance/area optimized bfloat16 adder and multiplication.
Over 60 figures and diagrams of LLMs, quantization, low-rank adapters (LoRA), and chat templates FREE TO USE in your blog posts, slides, presentations, or papers.
Convert PyTorch checkpoints, safetensors files and whole Hugging Face model folders to fp16, bf16, fp8 or ComfyUI fp8_scaled, int8_convrot and int8, turn FP8 models (DeepSeek, Qwen) back into BF16 on a CPU, merge or split sharded safetensors, and extract EMA weights, with one command and without loading the model into RAM.
Lossless compression of BF16 LLM weights, outputs bit-identical to the original. MLX on Apple Silicon and NVIDIA GPUs.
SplitZip: Ultra Fast Lossless KV Compression for Disaggregated LLM Serving
Fast BF16 PyTorch training operators for standard and low-rank Attention Residuals
Systematic 24-hour benchmark study of Qwen3.6-27B inference on dual NVIDIA RTX PRO 6000 Blackwell SM120 (TP=2). 8 experiments comparing repne/vllm fork vs upstream vLLM across FP8/BF16/NVFP4/Q8_0 quants and MTP/DFlash speculative decoding. Peak: 2,083 tok/s at c=32. Quality: KLD vs BF16 = 0.0018 (noise floor).
Converts a floating-point number or hexadecimal representation of a floating-point numbers into various formats and displays them into binary/hexadecimal.
Neural Weight Compression: lossless LLM weight compression decoded inside the CUDA matvec. BF16 31 % smaller and faster than cuBLAS; fp8 13 % smaller at native fp8 speed. Bit-identical weights.
Rust based converter for BF16 safetensors to Halogen v2 format
Python implementations for multi-precision quantization in computer vision and sensor fusion workloads, targeting the XR-NPE Mixed-Precision SIMD Neural Processing Engine. The code includes visual inertial odometry (VIO), object classification, and eye gaze extraction code in FP4, FP8, Posit4, Posit8, and BF16 formats.
ComfyUI Qwen-Image 2.1 multi-GPU inference: Ulysses sequence parallelism for 1/2/4/8 GPUs, T2I, image editing, INT8/FP8, and distributed prefix cache.
Auto GGUF Converter for HuggingFace Hub Models with Multiple Quantizations (GGUF Format)
Matrix-free 3D SIMP topology optimization with fused gather-GEMM-scatter CUDA kernels on NVIDIA RTX 4090. Companion code for arXiv:2604.18020.
DeepSeek-OCR-experimental is an advanced, multi-purpose visual document intelligence and object localization sandbox. Powered by the unredacted prithivMLmods/DeepSeek-OCR-Latest-BF16.I64-v2.0 architecture, this suite is designed to deliver highly accurate, structure-aware image text extractions.
Open, reproducible AMD XDNA1 + Strix Point XDNA2 compute on Linux: pinned builds, CPU-reference checks, persistent C/Python runners, and an LLM roadmap.
Lossless AI model compression - ~34% smaller with bit-identical weights; the autopilot profiles your machine, picks the highest fidelity that runs, and streams models bigger than your RAM.
A TPU-native tiled tensor data structure in Rust: the Padded Tile Lattice — sublane/lane layout, bf16/int8 dtypes, and a CPU reference simulator of systolic dataflow.
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