Open-source multi-channel DDR DMA controller for FPGA: 4 write channels, 5 read channels, async FIFOs, address generation, and arbitration.
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Updated
Oct 26, 2026 - HTML
Open-source multi-channel DDR DMA controller for FPGA: 4 write channels, 5 read channels, async FIFOs, address generation, and arbitration.
This is a demo code is to provide support for the Curiosity High Pin Count (HPC) development board using the PIC18F47Q10.
These labs provide support for the Curiosity High Pin Count (HPC) development board using the PIC18F46Q71.
Hall Sensor-based Trapezoidal Commutation for BLDC Motor with Hall Sequence Identifier(AN957)
Hall Sensor-based Trapezoidal Commutation for BLDC Motor with Hall Sequence Identifier(AN957)
Go SDK for CenturyLink Cloud API v1 (https://www.ctl.io/api-docs/v1)
PIC18F-Q84 Curiosity High Pin Count (HPC) Development board basic code examples.
Go SDK for CenturyLink Cloud API v2 (https://www.ctl.io/api-docs/v2)
SMC CLC Handshake Parser
Go bindings for CLC Cloud Application Manager (https://www.ctl.io/cloud-application-manager/)
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