rtl-design

⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

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Public RTL Question Bank of MakerCode https://makercode.jixiao-ai.com/

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JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

Pulse is a multi-platform digital logic simulation engine for VHDL made with C++. It transforms VHDL source code into logic components so it can be simulated and debugged.

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

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VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.

Gatery, a library for circuit design.

5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, ASIC-flowed, FPGA synthesized

ASIC and FPGA Design AI Skills

Claude Code skills & agents that automate a full RTL/Verilog design flow - architecture, RTL coding, lint, simulation, self-checking testbenches, regression, debug, Vivado synthesis, and docs - driven from a one-page IP spec.