An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Scala 2.4k 933
An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast
Python 116 35
Berkeley's Spatial Array Generator
Scala 1.5k 304
Hammer: Highly Agile Masks Made Effortlessly from RTL
Python 329 82
A Heterogeneous GPU Platform for AI and Neural Graphics
Scala 71 8
Chisel RISC-V Vector 1.0 Implementation
Assembly 159 42
Blast your models
Radiance 2 trace processing and visualization
MLIR dialect for Atlas.
MLIR-in as a compiler stack for ucb-bar
Software kernels for the Radiance GPU
Radiance 2 architecture simulator
An open-source UCIe implementation
Loading…
There was an error while loading. Please reload this page.